Mux

- Main Page
- Design Unit List
- Files

- Design Unit List
- Design Units
- Design Unit Members

Ports
mux_using_with Entity Reference

Mux entity brief description. More...

List of all members.

## Entities

behavior | architecture
| Architure definition of the MUX. More...

## Ports

din_0 | in std_logic
| Mux first input.
din_1 | in std_logic
| Mux Second input.
sel | in std_logic
| Select input.
mux_out | out std_logic
| Mux output.

## Detailed Description

Mux entity brief description.

Detailed description of this mux design element.

The documentation for this class was generated from the following file:

- mux.vhdl