## D. Using the Verga Simulator in Stand-Alone Mode

While Verga was written to support use through the TkGate graphical interface, it is possible to use Verga by itself in stand-alone mode. The input files need not be TkGate generated Verilog, and can be arbitrary Verilog code, as long as it uses only the subset of constructs supported by Verga.

To invoke Verga, use a command of the form:

`verga`[options] [files]

The supported options are:

Option | Description
--- | ---

`-i` | Interactive mode - In this mode, Verga will continue to read from the standard input while the simulation is running to accept commands controlling the simulation. This is the mode that the TkGate GUI uses when invoking Verga, and is generally only useful to TkGate.
`-e` | List error messages - Dump a list of all the error messages that Verga can generate.
`-l` | Show License - Print out the license information to the screen.
`-S` script | Load Script - Load a simulation script on start-up. This switch can be specified multiple times to load multiple scripts.

`-W` mode

Warning Mode - Sets the warning mode indicating how warnings are to be treated. Mode is a numeric value between 1 and 4. If mode is 1, warning will be ignored. If mode is 2, warnings will be reported only if there are errors. If mode is 3, warnings will always be reports. If mode is 4, warnings will be treated as errors, and the simulator will not start if there are warnings. The default mode value is 3.

`-s` | Scan Mode - Scans the modules in the input file and reports the names of the modules, and the variables declared in them. No simulation is performed.
`-q` | Quite Mode - Suppress printing of unnecessary messages.
`-P` | Print Modules - Echos back the input file from the internal parsed data.
`-B` dir | Base Directory - Makes dir the default directory when searching for files.
`-t` name | Set Top Module - Makes name the top-level module rather than automatically selecting one.
`-d` type | Delay Type - Sets the delay values to use. type can be one of `min`, `max` or `typical`.

Verga will scan all Verilog files specified on the command line. If the `-t` switch is not used to specify the top-level module, Verga will assume that the first module with no ports is the top-level module. Any output generated by the simulation is printed to the screen.

If you are using Verga to simulate a file saved from TkGate, you must be sure that you have enabled "Include cells in save files" from the General Options dialog box. If you do not, Verga will be unable to find the definitions for TkGate's built-in devices.