## C. List of Simulator Error Messages

### C.1 Run-Time Warnings/Errors

- Attempt to write to memory mem with unknown address. - Assigning a value to a memory (e.g, "`reg [7:0] mem[0:1023]`") with unknown bits in the address potentially invalidates the entire memory since there is no way of knowing which word was written to. This message informs you that such an attempt was made. The memory is not modified. This error message is not issued if the memory is completely uninitialized.
- Attempt to write to memory mem with unknown bit-range. - The bit-range given for a write to a memory contained unknown bits. For example, given the memory "`reg [7:0] mem[0:1023]`", the statement "`mem[10'h0][8'hx +: 3] = 3'b0;`" will generate this error message.
- Attempt to close non-open descriptor in task 'task'. - This error is generated when you call the `$fclose` system task with a descriptor that references files that are not open.
- Divide by zero. - A floating-point divide by zero was attempted.
- Execution of protected system task 'task' blocked. - The current security settings forbid the use of the task task. Attempts to execute that task result in issuing this error message and ignoring the system task call.
- Failed to load source file 'file'. - One of the files on the Verga command line could not be read.
- Failed to open memory file 'file'. - A file specified either through the interface or through a `$memreadb` or `$memreadh` system task could not be read.
- Illegal start value in task 'task'. - The start value in a `$readmem(b/h)` or `$writemem(b/h)` task was illegal.
- Illegal stop value in $readmemb. - The stop value in a `$readmem(b/h)` task was illegal.
- Simulation stopped on attempted execution of protected system task 'task'. - The design attempted to execute system task "task" while the current security settings are set to stop the simulation on any attempts to execute that task.
- Timing violation at line in inst[module] constrain. - This error is generated when a timing constrain specified in a `specify` block was violated. The line number in the code (line) is given with the instance name (inst), module name (module), and the constraint that was violated (constraint).

### C.2 Compile-Time Warnings

- Port size mismatch on input port 'A'. - The declared bit-size of input port "A" in the internal and external definitions of the target module do not match.
- Port size mismatch on output port 'A'. - The declared bit-size of output port "A" in the internal and external definitions of the target module do not match.
- Net 'A' has no drivers (floating net). - The net "A" has no gates that drive it to a value.
- Direct connect operator '=>' unsupported. Treated as '*>'. - A `specify` block is using the "=>" operator, but this operator not currently supported in the TkGate simulator.

### C.3 Compile-Time Errors

- Array 'mem' used in expression without index. - A variable that was defined as a memory/array such as "`reg [7:0] mem[0:1023]`" was used in an expression without an index. For example, "r = mem + 4;" would generate this error message.
- Array 'mem' used without index on left-hand-side. - A variable that was defined as a memory/array such as "`reg [7:0] mem[0:1023]`" was used in the left-hand side of an assignment without an index. For example, "mem = r;" would generate this error message.
- Auto range [*] is only valid with 'wire' declaration. - You can implicitly set the range in a wire declaration such as "`wire [*] w = 8'h0;`". This style of declaration is only valid for `wire` variables. If you attempt this type of declaration with any other variable type you will get this error.
- Bad gate instance range expression. - Primitive Verilog gates can take an bit-range to make them operate over multiple bits using the syntax "`and g1[3:0] (z,b,c);`". If the range expression `[3:0]` contains errors, this message will be produced.
- Bit-ranges on path delay specifiers unsupported. - A path delay in a `specify` block referenced individual bits in a signal. This feature is not supported by Verga.
- Delay and trigger expressions not allowed in path-delay modules. - Modules using path-delay declarations in a `specify` block can only be used to define combination logic. You can not use "`#`num" or "`@(`expr`)`" event control expressions.
- Design contains some modules with `timescale and some without. - You must use the ``timescale` directive with all modules or none of the modules.
- Event on multi-bit net 'a' can not have posedge/negedge. - You can not use the `posedge` and `negedge` keywords in a event trigger on a multi-bit signal. For example, if `a` is a multi-bit wire, then `@(posedge a)` would cause this error.
- Event wait on assign is illegal. - You attempted to use the `@(signal)` event trigger in an `assign` statement.
- Expecting identifier for argument arg of task 'task'. - You attempted to pass an expression or constant argument to a parameter of a task that requires a net be specified.
- Expression operator error in 'op'. - The operands used by op where illegal.
- Found module 'mod1' when expecting 'mod2'. - The module name specified after `module` keyword does not match the name of the module that was opened in the TkGate HDL module editor.
- Function 'func' used as task. - The identifier func was defined with the `function` keyword, but is used like a `task`.
- Hierarchical variable 'var' referenced in illegal context. - A hierarchical variable (one containing the "." character) was used in a context were they are forbidden such as in a `specify` block.
- Identifier 'a' in constant expression is not a parameter. - The non-parameter variable "a" was used in an expression that must be evaluated at compile time.
- Illegal address range on port 'p'. - The address range specified on a module port was illegal.
- Illegal address range specification 'range'. - The indicated address range was illegal.
- Illegal character (num) 'char'. - The input file contained a character that is not legal in the Verilog language.
- Illegal declaration of memory 'mem' in path-delay module - unsupported. - Modules using path-delay declarations in a `specify` block can only be used to define combination logic. Memories and register variables can not be used in such modules.
- Illegal event control expression. - The expression in an event control statement was illegal. For example "`@(4);`" will generate this error.
- Illegal redefinition of net 'net'. - The specified net was declared more than once in the same module.
- Inout connections must be net-to-net on port 'A'. - You specified an expression as the value of an `inout` port.
- Instance of undefined module 'mod'. - You attempted to include an instance of the module mod, but that module is not defined in your design.
- Invalid left-hand-side in 'assign'. - The left-hand side of an `assign` statement was illegal.
- Illegal use of '`v`' in left-hand-side of assignment. - `v` was used in a procedural assignment, but `v` is not a register type.
- Invalid left-hand-side in assignment. - The left-hand-side in a procedural assignment is invalid.
- Invalid output assignment. - An error occurred while generating an implicit `assign` statement for a module port.
- Invalid scale 'num' in `timescale declaration (must be 1, 10 or 100). - The numeric portion of the units or precision value must be a 1, 10 or 100, but a different value was used.
- Invalid syntax in `timescale declaration. - A ``timescale` directive was use with invalid syntax. A valid ``timescale` directive has the form "``timescale 1ns / 1 ns`".
- Invalid type declaration used on port 'port'. - The port port was declared with a type other than input, output or inout.
- Invalid units 'units' in `timescale declaration. - The units specified in a ``timescale` directive were illegal. The supported units are `s, ms, us, ns, ps` and `fs`.
- Loops in path-delay modules are unsupported. - Modules using path-delay declarations in a `specify` block can only be used to define combination logic. A feedback loop was detected in the module definition.
- Memories must be declared as register. - You attempted a declaration such as "`wire [7:0] mem[0:1023];`" which is illegal.
- Mixed named and unnamed ports on interface 'intf' of 'mod'. - When declaring module instance you must either use the `.`port`()` notation for all ports, or for none of the ports.
- <n>Mixed named and unnamed parameters on interface 'intf' of 'mod'.</n> When declaring module instance you must either use the `.`port`()` notation for all parameters, or for none of the parameters.
- More than one default: in case statement. - A case statement has more than one `default:` branch in it.
- Multiple assignment of net 'net' in path-delay module is unsupported. - Modules using path-delay declarations in a `specify` block can only be used to define combination logic. Assigning the same net more than once is not supported.
- Must specify posedge or negedge on event for A. - The `$setup`, `$hold$` and `$width` timing check tasks require that the reference event use either a `posedge` or a `negedge`. This error indicates that that keyword was missing.
- Net 'net' has no driver and is not an input in path-delay module. - Modules using path-delay declarations in a `specify` block can only be used to define combination logic. The net net is used in a path-delay module, but has no gates driving it.
- No current memory in memory file read. - A memory was loaded through the interface or through a `$memreadb` or `$memreadh` system task, but no memory was specified with the operation and there was no `@memory` declaration in the memory file.
- No matching `ifdef/`ifndef for decl declaration. - An ``endif`, ``else` or ``elseif` was found without a matching ``ifdef` or ``ifndef`.
- Non-blocking assignments to memories not implemented. - Verga only supports blocking assignments to arrays/memories using the "`=`" operator. The offending line used the "`<=`" operator to make an assignment to an array/memory.
- Non-register type used in task or function. - Tasks and functions can only declare and assign to register-type variables.
- Only input ports are allowed on functions. - A `function` was declared with ports other than `input` ports.
- Parameter 'port' is not declared as a port. - An instance of a module is passed a parameter that is not declared in the parameter list for that module. For example, "`foo #(.X(2)) f1(a,b);`" was used, but "`X`" is not declared as a parameter of `foo`.
- Parameter redefines identifier 'name'. - The variable name was defined as a `parameter`, but it has already been previously defined as something else.
- Port 'port' on interface 'intf' is not defined in module 'mod'. - A "`.`port`()`" was used in an instantiation of module mod, but port is not defined as a port on module mod.
- Port 'port' has no connections on interface 'intf' of 'mod'. - The port port defined as a port on module mod was not connected to anything when instantiating it in another module.
- Port 'port' has multiple connections on interface 'intf' of 'mod'. - Two "`.`port`()`" expressions with the same port name were used in the same module instance.
- Port count does not match definition on interface 'intf' of 'mod'. - The number of ports used in an instance of mod does not match the number of ports in the definition of mod.
- Range specification not allowed for memory reference of 'A'. - An attempt was made to reference multiple words of a memory at once. For example, a memory declared as "`reg [7:0] mem[0:1023]`" was referenced as "`mem[0:1]`".
- Redefinition of task or function 'task' in module 'mod'. - There is more than one definition of task in the module mod.
- Specified net 'net' is not a memory. - An attempt was made to read or write to net as a memory. Usually caused by the `$readmem(b/h)` or `$writemem(b/h)` system tasks.
- Syntax error. - The parser could not understand the syntax of a statement or expression.
- Task 'task' called with wrong number of arguments. - The number of arguments in a call to task does not match the number of arguments in the definition of task.
- Task 'task' can not be used in a specify block. - A task other than a constraint task such as `$setup`, `$hold` or `$width` was used in the context of a `specify` block.
- Task 'task' must be used in a specify block. - A constraint task such as `$setup`, `$hold` or `$width` was used outside the context of a `specify` block.
- Task 'task' used as function. - The identifier task was defined with the `task` keyword, but is used like a `function`.
- Too few parameter ports on instance inst. - An instance uses a parameter port list such as "`#(2, 3)`" without explicit parameter names, but the number of parameters specified is fewer than the number of parameters on the module definition.
- Too many files open in task 'task'. - Task task attempted to open a file when the maximum of 31 files are already open.
- Too many parameter ports on instance A. - An instance uses a parameter port list such as "`#(2, 3)`" without explicit parameter names, but the number of parameters specified is more than the number of parameters on the module definition.
- Top-module 'mod' not defined. - "mod" was designated as the top-module, but that module is not defined.
- Unable to open output file 'file' in task 'task'. - Task task attempted to open the file "file", but the open failed (e.g., because the user did not have write access).
- Undefined net 'net' in event control expression. - A control expression such as "`@(`net`)`" was used, but net is not defined.
- Undefined task 'task'. - An attempt was made to invoke a task that was not defined either as a system task or as a user task.
- Undefined variable 'var'. - An attempt was made to use a variable that was not defined.
- Units must be larger than precision in `timescale declaration. - The value specified as the units (the first number) in a ``timescale` must be larger than the precision (second number).
- Unsupported bit range [range] on net net (must be of form [n:0]). - Verga only supports bit ranges were 0 is the least significant bit. An attempt was made to declare a net with a unsupported bit range such as `[0:7]` or `[8:1]`.
- Unimplemented primitive gate instance type. - An attempt was made to use a Verilog primitive gate that Verga does not support such as "`tran`".
- Use of 'inout' in module with path-delay specification is unsupported. - Modules using path-delay declarations in a `specify` block can only be used to define combination logic. `inout` ports can not be used in such modules.
- Write to closed descriptor. - A system task was called that attempted to write to a descriptor that does not reference an open file.
- Wrong number of ports on primitive gate instance 'prim'. - A Verilog primitive gate was used with an incorrect number of ports. For example, an `and` was used with a single port, or a `bufif1` was used with other than three ports.